Distributed Reversi: Post-silicon Validation in Memory Subsystem for Multi-core Microprocessor

Post-silicon validation has always been an integral and crucial phase of microprocessor design and manufacturing process. As technology shrinks and processor becomes more complex, the difficulty has significantly increased in validation for multi-core micro-processor. Ilya Wangner and Valeria Bertacco proposed Reversi, a post-silicon validation system for single core microprocessor in 2008, which generates random programs in such a way that their correct final state is known at the beginning of the program. In this paper we propose a method to extend the application of Reversi to multi-core microprocessor. Our framework, called Distributed Reversi (DR), creates a multithreaded reversible program that runs on multi-core microprocessor, which takes advantage of shared memory for data forwarding. Such inter-core communication enables bugs exposure in memory subsystem. The experimental results show Distributed Reversi can detect 5 out of 11 bugs injected in Gem5 simulator memory subsystem.